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Source code

VP2INTERSECTD, VP2INTERSECTQ

Compute Intersection Between DWORDS/QUADWORDS to a

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.NDS.128.F2.0F38.W0 68 /rVP2INTERSECTD k1+1, xmm2, xmm3/m128/m32bcstAValidValidStore, in an even/odd pair of mask registers, AVX512_VP2INTERSECT the indicators of the locations of value matches between dwords in xmm3/m128/m32bcst and xmm2.
EVEX.NDS.256.F2.0F38.W0 68 /rVP2INTERSECTD k1+1, ymm2, ymm3/m256/m32bcstAValidValidStore, in an even/odd pair of mask registers, AVX512_VP2INTERSECT the indicators of the locations of value matches between dwords in ymm3/m256/m32bcst and ymm2.
EVEX.NDS.512.F2.0F38.W0 68 /rVP2INTERSECTD k1+1, zmm2, zmm3/m512/m32bcstAValidValidStore, in an even/odd pair of mask registers, AVX512_VP2INTERSECT the indicators of the locations of value matches between dwords in zmm3/m512/m32bcst and zmm2.
EVEX.NDS.128.F2.0F38.W1 68 /rVP2INTERSECTQ k1+1, xmm2, xmm3/m128/m64bcstAValidValidStore, in an even/odd pair of mask registers, AVX512_VP2INTERSECT the indicators of the locations of value matches between quadwords in xmm3/m128/m64bcst and xmm2.
EVEX.NDS.256.F2.0F38.W1 68 /rVP2INTERSECTQ k1+1, ymm2, ymm3/m256/m64bcstAValidValidStore, in an even/odd pair of mask registers, AVX512_VP2INTERSECT the indicators of the locations of value matches between quadwords in ymm3/m256/m64bcst and ymm2.
EVEX.NDS.512.F2.0F38.W1 68 /rVP2INTERSECTQ k1+1, zmm2, zmm3/m512/m64bcstAValidValidStore, in an even/odd pair of mask registers, AVX512_VP2INTERSECT the indicators of the locations of value matches between quadwords in zmm3/m512/m64bcst and zmm2.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

This instruction writes an even/odd pair of mask registers. The mask register destination indicated in the MODRM.REG field is used to form the basis of the register pair. The low bit of that field is masked off (set to zero) to create the first register of the pair.

EVEX.aaa and EVEX.z must be zero.

Operation

VP2INTERSECTD destmask, src1, src2
(KL, VL) = (4, 128), (8, 256), (16, 512)

// dest_mask_reg_id is the register id specified in the instruction for destmask
dest_base := dest_mask_reg_id & ~1

// maskregs[ ] is an array representing the mask registers
maskregs[dest_base+0][MAX_KL-1:0] := 0
maskregs[dest_base+1][MAX_KL-1:0] := 0

FOR i := 0 to KL-1:
    FOR j := 0 to KL-1:
         match := (src1.dword[i] == src2.dword[j])
          maskregs[dest_base+0].bit[i] |= match
          maskregs[dest_base+1].bit[j] |= match

VP2INTERSECTQ destmask, src1, src2
(KL, VL) = (2, 128), (4, 256), (8, 512)

// dest_mask_reg_id is the register id specified in the instruction for destmask
dest_base := dest_mask_reg_id & ~1

// maskregs[ ] is an array representing the mask registers
maskregs[dest_base+0][MAX_KL-1:0] := 0
maskregs[dest_base+1][MAX_KL-1:0] := 0

FOR i = 0 to KL-1:
    FOR j = 0 to KL-1:
         match := (src1.qword[i] == src2.qword[j])
          maskregs[dest_base+0].bit[i] |= match
          maskregs[dest_base+1].bit[j] |= match

Intel C/C++ compiler intrinsics

VP2INTERSECTD void _mm_2intersect_epi32(__m128i, __m128i, __mmask8 *, __mmask8 *);
VP2INTERSECTD void _mm256_2intersect_epi32(__m256i, __m256i, __mmask8 *, __mmask8 *);
VP2INTERSECTD void _mm512_2intersect_epi32(__m512i, __m512i, __mmask16 *, __mmask16 *);
VP2INTERSECTQ void _mm_2intersect_epi64(__m128i, __m128i, __mmask8 *, __mmask8 *);
VP2INTERSECTQ void _mm256_2intersect_epi64(__m256i, __m256i, __mmask8 *, __mmask8 *);
VP2INTERSECTQ void _mm512_2intersect_epi64(__m512i, __m512i, __mmask8 *, __mmask8 *);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-52, "Type E4NF Class Exception Conditions."

Sources