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Source code

VPSHLD

Concatenate and Shift Packed Data Left Logical

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F3A.W1 70 /r /ibVPSHLDW xmm1{k1}{z}, xmm2, xmm3/m128, imm8AValidValidConcatenate destination and source operands, AND AVX512VL) extract result shifted to the left by constant OR AVX10.1 value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 70 /r /ibVPSHLDW ymm1{k1}{z}, ymm2, ymm3/m256, imm8AValidValidConcatenate destination and source operands, AND AVX512VL) extract result shifted to the left by constant OR AVX10.1 value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 70 /r /ibVPSHLDW zmm1{k1}{z}, zmm2, zmm3/m512, imm8AValidValidConcatenate destination and source operands, OR AVX10.1 extract result shifted to the left by constant value in imm8 into zmm1.
EVEX.128.66.0F3A.W0 71 /r /ibVPSHLDD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst, imm8BValidValidConcatenate destination and source operands, AND AVX512VL) extract result shifted to the left by constant OR AVX10.1 value in imm8 into xmm1.
EVEX.256.66.0F3A.W0 71 /r /ibVPSHLDD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8BValidValidConcatenate destination and source operands, AND AVX512VL) extract result shifted to the left by constant OR AVX10.1 value in imm8 into ymm1.
EVEX.512.66.0F3A.W0 71 /r /ibVPSHLDD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8BValidValidConcatenate destination and source operands, OR AVX10.1 extract result shifted to the left by constant value in imm8 into zmm1.
EVEX.128.66.0F3A.W1 71 /r /ibVPSHLDQ xmm1{k1}{z}, xmm2, xmm3/m128/m64bcst, imm8BValidValidConcatenate destination and source operands, AND AVX512VL) extract result shifted to the left by constant OR AVX10.1 value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 71 /r /ibVPSHLDQ ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8BValidValidConcatenate destination and source operands, AND AVX512VL) extract result shifted to the left by constant OR AVX10.1 value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 71 /r /ibVPSHLDQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8BValidValidConcatenate destination and source operands, OR AVX10.1 extract result shifted to the left by constant value in imm8 into zmm1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  4. imm8 lecturaimmediate byte after the instruction

Tupla: Full Mem

B

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  4. imm8 lecturaimmediate byte after the instruction

Tupla: Full

Measured cost

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Description

Concatenate packed data, extract result shifted to the left by constant value. This instruction supports memory fault suppression.

Operation

VPSHLDW DEST, SRC2, SRC3, imm8
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:

    IF MaskBit(j) OR *no writemask*:
          tmp := concat(SRC2.word[j], SRC3.word[j]) << (imm8 & 15)
          DEST.word[j] := tmp.word[1]

    ELSE IF *zeroing*:
          DEST.word[j] := 0

    *ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0

VPSHLDD DEST, SRC2, SRC3, imm8
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:

    IF SRC3 is broadcast memop:
          tsrc3 := SRC3.dword[0]

    ELSE:
          tsrc3 := SRC3.dword[j]

    IF MaskBit(j) OR *no writemask*:
          tmp := concat(SRC2.dword[j], tsrc3) << (imm8 & 31)
          DEST.dword[j] := tmp.dword[1]

    ELSE IF *zeroing*:
          DEST.dword[j] := 0

    *ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0

VPSHLDQ DEST, SRC2, SRC3, imm8
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:

    IF SRC3 is broadcast memop:
          tsrc3 := SRC3.qword[0]

    ELSE:
          tsrc3 := SRC3.qword[j]

    IF MaskBit(j) OR *no writemask*:
          tmp := concat(SRC2.qword[j], tsrc3) << (imm8 & 63)
          DEST.qword[j] := tmp.qword[1]

    ELSE IF *zeroing*:
          DEST.qword[j] := 0

    *ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPSHLDD __m128i _mm_shldi_epi32(__m128i, __m128i, int);
VPSHLDD __m128i _mm_mask_shldi_epi32(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDD __m128i _mm_maskz_shldi_epi32(__mmask8, __m128i, __m128i, int);
VPSHLDD __m256i _mm256_shldi_epi32(__m256i, __m256i, int);
VPSHLDD __m256i _mm256_mask_shldi_epi32(__m256i, __mmask8, __m256i, __m256i, int);
VPSHLDD __m256i _mm256_maskz_shldi_epi32(__mmask8, __m256i, __m256i, int);
VPSHLDD __m512i _mm512_shldi_epi32(__m512i, __m512i, int);
VPSHLDD __m512i _mm512_mask_shldi_epi32(__m512i, __mmask16, __m512i, __m512i, int);
VPSHLDD __m512i _mm512_maskz_shldi_epi32(__mmask16, __m512i, __m512i, int);
VPSHLDQ __m128i _mm_shldi_epi64(__m128i, __m128i, int);
VPSHLDQ __m128i _mm_mask_shldi_epi64(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDQ __m128i _mm_maskz_shldi_epi64(__mmask8, __m128i, __m128i, int);
VPSHLDQ __m256i _mm256_shldi_epi64(__m256i, __m256i, int);
VPSHLDQ __m256i _mm256_mask_shldi_epi64(__m256i, __mmask8, __m256i, __m256i, int);
VPSHLDQ __m256i _mm256_maskz_shldi_epi64(__mmask8, __m256i, __m256i, int);
VPSHLDQ __m512i _mm512_shldi_epi64(__m512i, __m512i, int);
VPSHLDQ __m512i _mm512_mask_shldi_epi64(__m512i, __mmask8, __m512i, __m512i, int);
VPSHLDQ __m512i _mm512_maskz_shldi_epi64(__mmask8, __m512i, __m512i, int);
VPSHLDW __m128i _mm_shldi_epi16(__m128i, __m128i, int);
VPSHLDW __m128i _mm_mask_shldi_epi16(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDW __m128i _mm_maskz_shldi_epi16(__mmask8, __m128i, __m128i, int);
VPSHLDW __m256i _mm256_shldi_epi16(__m256i, __m256i, int);
VPSHLDW __m256i _mm256_mask_shldi_epi16(__m256i, __mmask16, __m256i, __m256i, int);
VPSHLDW __m256i _mm256_maskz_shldi_epi16(__mmask16, __m256i, __m256i, int);
VPSHLDW __m512i _mm512_shldi_epi16(__m512i, __m512i, int);
VPSHLDW __m512i _mm512_mask_shldi_epi16(__m512i, __mmask32, __m512i, __m512i, int);
VPSHLDW __m512i _mm512_maskz_shldi_epi16(__mmask32, __m512i, __m512i, int);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-51, "Type E4 Class Exception Conditions."

Sources