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Source code

KSHIFTLW, KSHIFTLB, KSHIFTLQ, KSHIFTLD

Shift Left Mask Registers

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
VEX.L0.66.0F3A.W1 32 /rKSHIFTLW k1, k2, imm8RRIValidValidShift left 16 bits in k2 by immediate and write result in k1. OR AVX10.1
VEX.L0.66.0F3A.W0 32 /rKSHIFTLB k1, k2, imm8RRIValidValidShift left 8 bits in k2 by immediate and write result in k1. OR AVX10.1
VEX.L0.66.0F3A.W1 33 /rKSHIFTLQ k1, k2, imm8RRIValidValidShift left 64 bits in k2 by immediate and write result in k1. OR AVX10.1
VEX.L0.66.0F3A.W0 33 /rKSHIFTLD k1, k2, imm8RRIValidValidShift left 32 bits in k2 by immediate and write result in k1. OR AVX10.1

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RRI

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  3. imm8immediate byte after the instruction

Measured cost

Loading measurements from arch-data...

Description

Shifts 8/16/32/64 bits in the second operand (source operand) left by the count specified in immediate byte and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).

Operation

KSHIFTLW
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=15

    THEN DEST[15:0] := SRC1[15:0] << COUNT;
FI;

KSHIFTLB

COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=7

            THEN DEST[7:0] := SRC1[7:0] << COUNT;
FI;

KSHIFTLQ

COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=63

            THEN DEST[63:0] := SRC1[63:0] << COUNT;
FI;


KSHIFTLD
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=31

            THEN DEST[31:0] := SRC1[31:0] << COUNT;
FI;

Flags affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, "TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)."

Sources