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FLD

Load Floating-Point Value

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
D9 /0FLD m32fpValidValidPush m32fp onto the FPU register stack.
DD /0FLD m64fpValidValidPush m64fp onto the FPU register stack.
DB /5FLD m80fpValidValidPush m80fp onto the FPU register stack.
D9 C0+iFLD ST(i)ValidValidPush ST(i) onto the FPU register stack.

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Description

Pushes the source operand onto the FPU register stack. The source operand can be in single precision, double precision, or double extended-precision floating-point format. If the source operand is in single precision or double precision floating-point format, it is automatically converted to the double extended-precision floating-point format before being pushed on the stack.

The FLD instruction can also push the value in a selected FPU register [ST(i)] onto the stack. Here, pushing register ST(0) duplicates the stack top.

NOTE

When the FLD instruction loads a denormal value and the DM bit in the CW is not masked, an exception is flagged but the value is still pushed onto the x87 stack.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation

IF SRC is ST(i)
    THEN
          temp := ST(i);

FI;

TOP := TOP - 1;

IF SRC is memory-operand
    THEN
          ST(0) := ConvertToDoubleExtendedPrecisionFP(SRC);
    ELSE (* SRC is ST(i) *)
          ST(0) := temp;

FI;

FPU Flags Affected

C1                  Set to 1 if stack overflow occurred; otherwise, set to 0.

C0, C2, C3          Undefined.

Floating-Point Exceptions

#IS                 Stack underflow or overflow occurred.
#IA                 Source operand is an SNaN. Does not occur if the source operand is in double extended-preci-

sion floating-point format (FLD m80fp or FLD ST(i)).

#D                  Source operand is a denormal value. Does not occur if the source operand is in double

extended-precision floating-point format.

Description

Push one of seven commonly used constants (in double extended-precision floating-point format) onto the FPU register stack. The constants that can be loaded with these instructions include +1.0, +0.0, log210, log2e, , log102, and loge2. For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control word) to double extended-precision floating-point format. The inexact-result exception (#P) is not generated as a result of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up.

See the section titled "Approximation of Pi" in Chapter 8 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of the constant.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

IA-32 architecture compatibility

When the RC field is set to round-to-nearest, the FPU produces the same constants that is produced by the Intel 8087 and Intel 287 math coprocessors.

Operation

TOP := TOP - 1;

ST(0) := CONSTANT;

FPU Flags Affected

C1                  Set to 1 if stack overflow occurred; otherwise, set to 0.

C0, C2, C3          Undefined.

Floating-Point Exceptions

#IS                 Stack overflow occurred.

Exceptions

Protected mode
#GP(0)If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
#SS(0)If a memory operand effective address is outside the SS segment limit.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UDIf the LOCK prefix is used.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
Real address mode
#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SSIf a memory operand effective address is outside the SS segment limit.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UDIf the LOCK prefix is used.
Same exceptions as in protected mode.
Virtual-8086 mode
#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)If a memory operand effective address is outside the SS segment limit.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made.
#UDIf the LOCK prefix is used.
Same exceptions as in protected mode.
Same exceptions as in protected mode.
Compatibility mode
Same exceptions as in protected mode.
Same exceptions as in protected mode.
64-bit mode
#SS(0)If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)If the memory address is in a non-canonical form.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UDIf the LOCK prefix is used. FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ--Load Constant Opcode* Instruction 64-Bit Compat/ Description Mode Leg Mode Valid Push +1.0 onto the FPU register stack. D9 E8 FLD1 Valid Valid Push log210 onto the FPU register stack. Valid Push log2e onto the FPU register stack. D9 E9 FLDL2T Valid Valid Push onto the FPU register stack. Valid Push log102 onto the FPU register stack. D9 EA FLDL2E Valid Valid Push loge2 onto the FPU register stack. Valid Push +0.0 onto the FPU register stack. D9 EB FLDPI Valid D9 EC FLDLG2 Valid D9 ED FLDLN2 Valid D9 EE FLDZ Valid NOTES: * See IA-32 Architecture Compatibility section below.
Same exceptions as in protected mode.

Sources