Vesta
English
Source code

KANDNW, KANDNB, KANDNQ, KANDND

Bitwise Logical AND NOT Masks

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
VEX.L1.0F.W0 42 /rKANDNW k1, k2, k3RVRValidValidBitwise AND NOT 16 bits masks k2 and k3 and place result in k1. OR AVX10.1
VEX.L1.66.0F.W0 42 /rKANDNB k1, k2, k3RVRValidValidBitwise AND NOT 8 bits masks k1 and k2 and place result in k1. OR AVX10.1
VEX.L1.0F.W1 42 /rKANDNQ k1, k2, k3RVRValidValidBitwise AND NOT 64 bits masks k2 and k3 and place result in k1. OR AVX10.1
VEX.L1.66.0F.W1 42 /rKANDND k1, k2, k3RVRValidValidBitwise AND NOT 32 bits masks k2 and k3 and place result in k1. OR AVX10.1

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RVR

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Performs a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.

Operation

KANDNW
DEST[15:0] := (BITWISE NOT SRC1[15:0]) BITWISE AND SRC2[15:0]
DEST[MAX_KL-1:16] := 0

KANDNB
DEST[7:0] := (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]
DEST[MAX_KL-1:8] := 0

KANDNQ
DEST[63:0] := (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64] := 0

KANDND
DEST[31:0] := (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]
DEST[MAX_KL-1:32] := 0

Intel C/C++ compiler intrinsics

KANDNW __mmask16 _mm512_kandn(__mmask16 a, __mmask16 b);

Flags affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, "TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)."

Sources