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Source code

VFPCLASSPH

Test Types of Packed FP16 Values

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.NP.0F3A.W0 66 /r /ibVFPCLASSPH k1{k2}, xmm1/m128/m16bcst, imm8AValidValidTest the input for the following categories: NaN, AND AVX512VL) +0, -0, +Infinity, -Infinity, denormal, finite OR AVX10.1 negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
EVEX.256.NP.0F3A.W0 66 /r /ibVFPCLASSPH k1{k2}, ymm1/m256/m16bcst, imm8AValidValidTest the input for the following categories: NaN, AND AVX512VL) +0, -0, +Infinity, -Infinity, denormal, finite OR AVX10.1 negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
EVEX.512.NP.0F3A.W0 66 /r /ibVFPCLASSPH k1{k2}, zmm1/m512/m16bcst, imm8AValidValidTest the input for the following categories: NaN, OR AVX10.1 +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  3. imm8 lecturaimmediate byte after the instruction

Tupla: Full

Measured cost

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Description

This instruction checks the packed FP16 values in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against; see Table 5-12 for the categories. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the corresponding bits in the destination mask register according to the writemask.

Classifier Operations for VFPCLASSPH/VFPCLASSSH

BitsCategoryClassifier
[0]QNANChecks for QNAN
[1]PosZeroChecks +0
[2]NegZeroChecks for -0
[3]PosINFChecks for +
[4]NegINFChecks for -
[5]DenormalChecks for Denormal

Operation

def check_fp_class_fp16(tsrc, imm8):

    negative := tsrc[15]
    exponent_all_ones := (tsrc[14:10] == 0x1F)
    exponent_all_zeros := (tsrc[14:10] == 0)
    mantissa_all_zeros := (tsrc[9:0] == 0)
    zero := exponent_all_zeros and mantissa_all_zeros
    signaling_bit := tsrc[9]

    snan := exponent_all_ones and not(mantissa_all_zeros) and not(signaling_bit)
    qnan := exponent_all_ones and not(mantissa_all_zeros) and signaling_bit
    positive_zero := not(negative) and zero
    negative_zero := negative and zero
    positive_infinity := not(negative) and exponent_all_ones and mantissa_all_zeros
    negative_infinity := negative and exponent_all_ones and mantissa_all_zeros
    denormal := exponent_all_zeros and not(mantissa_all_zeros)
    finite_negative := negative and not(exponent_all_ones) and not(zero)

    return (imm8[0] and qnan) OR
          (imm8[1] and positive_zero) OR
          (imm8[2] and negative_zero) OR
          (imm8[3] and positive_infinity) OR
          (imm8[4] and negative_infinity) OR
          (imm8[5] and denormal) OR
          (imm8[6] and finite_negative) OR
          (imm8[7] and snan)

VFPCLASSPH dest{k2}, src, imm8
VL = 128, 256 or 512
KL := VL/16

FOR i := 0 to KL-1:
    IF k2[i] or *no writemask*:
          IF SRC is memory and (EVEX.b = 1):
                tsrc := SRC.fp16[0]
          ELSE:
                tsrc := SRC.fp16[i]
          DEST.bit[i] := check_fp_class_fp16(tsrc, imm8)
    ELSE:
          DEST.bit[i] := 0

DEST[MAXKL-1:kl] := 0

Intel C/C++ compiler intrinsics

VFPCLASSPH __mmask8 _mm_fpclass_ph_mask (__m128h a, int imm8);
VFPCLASSPH __mmask8 _mm_mask_fpclass_ph_mask (__mmask8 k1, __m128h a, int imm8);
VFPCLASSPH __mmask16 _mm256_fpclass_ph_mask (__m256h a, int imm8);
VFPCLASSPH __mmask16 _mm256_mask_fpclass_ph_mask (__mmask16 k1, __m256h a, int imm8);
VFPCLASSPH __mmask32 _mm512_fpclass_ph_mask (__m512h a, int imm8);
VFPCLASSPH __mmask32 _mm512_mask_fpclass_ph_mask (__mmask32 k1, __m512h a, int imm8);

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instructions, see Table 2-51, "Type E4 Class Exception Conditions."

Sources