MOVSX, MOVSXD
Move With Sign-Extension
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
0F BE /r | MOVSX r16, r/m8 | RM | Valid | Valid | Move byte to word with sign-extension. |
0F BE /r | MOVSX r3, r/m8 | RM | Valid | Valid | Move byte to doubleword with signextension. |
REX.W + 0F BE /r | MOVSX r64, r/m8 | RM | Valid | Not encodable | Move byte to quadword with sign-extension. |
0F BF /r | MOVSX r3, r/m16 | RM | Valid | Valid | Move word to doubleword, with signextension. |
REX.W + 0F BF /r | MOVSX r64, r/m16 | RM | Valid | Not encodable | Move word to quadword with sign-extension. |
63 /r2 | MOVSXD r16, r/m16 | RM | Valid | Not encodable | Move word to word with sign-extension. |
63 /r2 | MOVSXD r3, r/m3 | RM | Valid | Not encodable | Move doubleword to doubleword with signextension. |
REX.W + 63 /r | MOVSXD r64, r/m3 | RM | Valid | Not encodable | Move doubleword to quadword with signextension. |
Operand encoding
Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.
RM
modrm.regescrituraModRM byte, reg field (bits 5-3)modrm.rmlecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
Measured cost
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Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1). The size of the converted value depends on the operand-size attribute.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST := SignExtend(SRC);Flags affected
None.
Exceptions
Protected mode
#GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used. |
Real address mode
#GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS | If a memory operand effective address is outside the SS segment limit. |
#UD | If the LOCK prefix is used. |
Virtual-8086 mode
#GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. |
#UD | If the LOCK prefix is used. |
Compatibility mode
| Same exceptions as in protected mode. |
64-bit mode
#SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
#GP(0) | If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used. |