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VPBROADCASTB, VPBROADCASTW, VPBROADCASTD, VPBROADCASTQ

Load With Broadcast Integer Data From General Purpose Register

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F38.W0 7A /rVPBROADCASTB xmm1 {k1}{z}, regAValidValidBroadcast an 8-bit value from a GPR to all bytes in AVX512BW) OR AVX10.1 the 128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7A /rVPBROADCASTB ymm1 {k1}{z}, regAValidValidBroadcast an 8-bit value from a GPR to all bytes in AVX512BW) OR AVX10.1 the 256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7A /rVPBROADCASTB zmm1 {k1}{z}, regAValidValidBroadcast an 8-bit value from a GPR to all bytes in OR AVX10.1 the 512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W0 7B /rVPBROADCASTW xmm1 {k1}{z}, regAValidValidBroadcast a 16-bit value from a GPR to all words in AVX512BW) OR AVX10.1 the 128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7B /rVPBROADCASTW ymm1 {k1}{z}, regAValidValidBroadcast a 16-bit value from a GPR to all words in AVX512BW) OR AVX10.1 the 256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7B /rVPBROADCASTW zmm1 {k1}{z}, regAValidValidBroadcast a 16-bit value from a GPR to all words in OR AVX10.1 the 512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W0 7C /rVPBROADCASTD xmm1 {k1}{z}, r32AValidValidBroadcast a 32-bit value from a GPR to all AVX512F) OR AVX10.1 doublewords in the 128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7C /rVPBROADCASTD ymm1 {k1}{z}, r32AValidValidBroadcast a 32-bit value from a GPR to all AVX512F) OR AVX10.1 doublewords in the 256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7C /rVPBROADCASTD zmm1 {k1}{z}, r32AValidValidBroadcast a 32-bit value from a GPR to all OR AVX10.1 doublewords in the 512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W1 7C /rVPBROADCASTQ xmm1 {k1}{z}, r64AValidn.e.1Broadcast a 64-bit value from a GPR to all AVX512F) OR AVX10.1 quadwords in the 128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W1 7C /rVPBROADCASTQ ymm1 {k1}{z}, r64AValidn.e.1Broadcast a 64-bit value from a GPR to all AVX512F) OR AVX10.1 quadwords in the 256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W1 7C /rVPBROADCASTQ zmm1 {k1}{z}, r64AValidn.e.1Broadcast a 64-bit value from a GPR to all OR AVX10.1 quadwords in the 512-bit destination subject to writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Tuple1 Scalar

Measured cost

Loading measurements from arch-data...

Description

Broadcasts a 8-bit, 16-bit, 32-bit or 64-bit value from a general-purpose register (the second operand) to all the locations in the destination vector register (the first operand) using the writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VPBROADCASTB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

     THEN DEST[i+7:i] := SRC[7:0]

     ELSE

             IF *merging-masking*           ; merging-masking

                 THEN *DEST[i+7:i] remains unchanged*

                 ELSE                       ; zeroing-masking

                    DEST[i+7:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPBROADCASTW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

     THEN DEST[i+15:i] := SRC[15:0]

     ELSE

             IF *merging-masking*           ; merging-masking

                 THEN *DEST[i+15:i] remains unchanged*

                 ELSE                       ; zeroing-masking

                    DEST[i+15:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPBROADCASTD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

     THEN DEST[i+31:i] := SRC[31:0]

     ELSE

             IF *merging-masking*           ; merging-masking

                 THEN *DEST[i+31:i] remains unchanged*

                 ELSE                       ; zeroing-masking

                    DEST[i+31:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0


VPBROADCASTQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

     THEN DEST[i+63:i] := SRC[63:0]

     ELSE

             IF *merging-masking*        ; merging-masking

                 THEN *DEST[i+63:i] remains unchanged*

                 ELSE                    ; zeroing-masking

                    DEST[i+63:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPBROADCASTB __m512i _mm512_mask_set1_epi8(__m512i s, __mmask64 k, int a);
VPBROADCASTB __m512i _mm512_maskz_set1_epi8( __mmask64 k, int a);
VPBROADCASTB __m256i _mm256_mask_set1_epi8(__m256i s, __mmask32 k, int a);
VPBROADCASTB __m256i _mm256_maskz_set1_epi8( __mmask32 k, int a);
VPBROADCASTB __m128i _mm_mask_set1_epi8(__m128i s, __mmask16 k, int a);
VPBROADCASTB __m128i _mm_maskz_set1_epi8( __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_mask_set1_epi32(__m512i s, __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_maskz_set1_epi32( __mmask16 k, int a);
VPBROADCASTD __m256i _mm256_mask_set1_epi32(__m256i s, __mmask8 k, int a);
VPBROADCASTD __m256i _mm256_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTD __m128i _mm_mask_set1_epi32(__m128i s, __mmask8 k, int a);
VPBROADCASTD __m128i _mm_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTQ __m512i _mm512_mask_set1_epi64(__m512i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m512i _mm512_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_mask_set1_epi64(__m256i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_mask_set1_epi64(__m128i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTW __m512i _mm512_mask_set1_epi16(__m512i s, __mmask32 k, int a);
VPBROADCASTW __m512i _mm512_maskz_set1_epi16( __mmask32 k, int a);
VPBROADCASTW __m256i _mm256_mask_set1_epi16(__m256i s, __mmask16 k, int a);
VPBROADCASTW __m256i _mm256_maskz_set1_epi16( __mmask16 k, int a);
VPBROADCASTW __m128i _mm_mask_set1_epi16(__m128i s, __mmask8 k, int a);
VPBROADCASTW __m128i _mm_maskz_set1_epi16( __mmask8 k, int a);

Sources