DIV

Unsigned Divide

stableVMJITAOTinstruction

Encodings

Opcode	Instruction	Op/En	64-bit	Compat/Legacy	Description
`F6 /6`	`DIV r/m8`	M	Valid	Valid	Unsigned divide AX by r/m8, with result stored in AL := Quotient, AH := Remainder.
`F7 /6`	`DIV r/m16`	M	Valid	Valid	Unsigned divide DX:AX by r/m16, with result stored in AX := Quotient, DX := Remainder.
`F7 /6`	`DIV r/m32`	M	Valid	Valid	Unsigned divide EDX:EAX by r/m32, with result stored in EAX := Quotient, EDX := Remainder.
`REX.W + F7 /6`	`DIV r/m64`	M	Valid	Not encodable	Unsigned divide RDX:RAX by r/m64, with result stored in RAX := Quotient, RDX := Remainder.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

M

modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Flags named

CF Carry
PF Parity
AF Auxiliary carry
ZF Zero
SF Sign
OF Overflow

Description

Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.

Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in RAX, the remainder in RDX.

See the summary chart at the beginning of this section for encoding data and limits. See Table 3-17.

DIV Action

Word/byte	AX	r/m8	AL	AH	255
Doubleword/word	DX:AX	r/m16	AX	DX	65,535
Quadword/doubleword	EDX:EAX	r/m32	EAX	EDX	232 - 1
Doublequadword/	RDX:RAX	r/m64	RAX	RDX	264 - 1
quadword
DIV--Unsigned Divide

Operation

IF SRC = 0

    THEN #DE; FI; (* Divide Error *)
IF OperandSize = 8 (* Word/Byte Operation *)

    THEN
          temp := AX / SRC;
          IF temp > FFH
                THEN #DE; (* Divide error *)
                ELSE
                       AL := temp;
                       AH := AX MOD SRC;
          FI;

   ELSE IF OperandSize = 16 (* Doubleword/word operation *)

          THEN
                temp := DX:AX / SRC;
                IF temp > FFFFH
                       THEN #DE; (* Divide error *)
                ELSE
                       AX := temp;
                       DX := DX:AX MOD SRC;
                FI;

          FI;
    ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)

          THEN
                temp := EDX:EAX / SRC;
                IF temp > FFFFFFFFH
                       THEN #DE; (* Divide error *)
                ELSE
                       EAX := temp;
                       EDX := EDX:EAX MOD SRC;
                FI;

          FI;
    ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)

          THEN
                temp := RDX:RAX / SRC;
                IF temp > FFFFFFFFFFFFFFFFH
                       THEN #DE; (* Divide error *)
                ELSE
                       RAX := temp;
                       RDX := RDX:RAX MOD SRC;
                FI;

          FI;
FI;

Flags affected

The CF, OF, SF, ZF, AF, and PF flags are undefined.

Exceptions

Protected mode

`#DE`	If the source operand (divisor) is 0 If the quotient is too large for the designated register.
`#GP(0)`	If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.
`#SS(0)`	If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
`#AC(0)`	If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
`#UD`	If the LOCK prefix is used.

Real address mode

`#DE`	If the source operand (divisor) is 0. If the quotient is too large for the designated register.
`#GP`	If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.
`#SS(0)`	If a memory operand effective address is outside the SS segment limit.
`#UD`	If the LOCK prefix is used.

Virtual-8086 mode

`#DE`	If the source operand (divisor) is 0. If the quotient is too large for the designated register.
`#GP(0)`	If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
`#SS`	If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
`#AC(0)`	If alignment checking is enabled and an unaligned memory reference is made.
`#UD`	If the LOCK prefix is used.

Compatibility mode

Same exceptions as in protected mode.

64-bit mode

`#SS(0)`	If a memory address referencing the SS segment is in a non-canonical form.
`#GP(0)`	If the memory address is in a non-canonical form.
`#DE`	If the source operand (divisor) is 0 If the quotient is too large for the designated register. #PF(fault-code) If a page fault occurs.
`#AC(0)`	If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
`#UD`	If the LOCK prefix is used.

DIV

Encodings

Operand encoding

M

Measured cost

Flags named

Description#

Operation#

Flags affected#

Exceptions

Sources

Description

Operation

Flags affected