Vesta
English
Source code

VPBLENDMD, VPBLENDMQ

Blend Int32/Int64 Vectors Using an OpMask Control

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F38.W0 64 /rVPBLENDMD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstAValidValidBlend doubleword integer vector xmm2 and AVX512F) OR doubleword vector xmm3/m128/m32bcst and AVX10.1 store the result in xmm1, under control mask.
EVEX.256.66.0F38.W0 64 /rVPBLENDMD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstAValidValidBlend doubleword integer vector ymm2 and AVX512F) OR doubleword vector ymm3/m256/m32bcst and AVX10.1 store the result in ymm1, under control mask.
EVEX.512.66.0F38.W0 64 /rVPBLENDMD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstAValidValidBlend doubleword integer vector zmm2 and OR AVX10.1 doubleword vector zmm3/m512/m32bcst and store the result in zmm1, under control mask.
EVEX.128.66.0F38.W1 64 /rVPBLENDMQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstAValidValidBlend quadword integer vector xmm2 and AVX512F) OR quadword vector xmm3/m128/m64bcst and store AVX10.1 the result in xmm1, under control mask.
EVEX.256.66.0F38.W1 64 /rVPBLENDMQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstAValidValidBlend quadword integer vector ymm2 and AVX512F) OR quadword vector ymm3/m256/m64bcst and store AVX10.1 the result in ymm1, under control mask.
EVEX.512.66.0F38.W1 64 /rVPBLENDMQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstAValidValidBlend quadword integer vector zmm2 and OR AVX10.1 quadword vector zmm3/m512/m64bcst and store the result in zmm1, under control mask.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

Performs an element-by-element blending of dword/qword elements between the first source operand (the second operand) and the elements of the second source operand (the third operand) using an opmask register as select control. The blended result is written into the destination.

The destination and first source operands are ZMM registers. The second source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location.

The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every element of the destination is conditionally selected between first source or second source using the value of the related mask bit (0 for the first source operand, 1 for the second source operand).

If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.

Operation

VPBLENDMD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no controlmask*

     THEN

             IF (EVEX.b = 1) AND (SRC2 *is memory*)

                  THEN

                    DEST[i+31:i] := SRC2[31:0]

                  ELSE

                    DEST[i+31:i] := SRC2[i+31:i]

             FI;

     ELSE

             IF *merging-masking*                 ; merging-masking

                  THEN DEST[i+31:i] := SRC1[i+31:i]

                  ELSE                            ; zeroing-masking

                    DEST[i+31:i] := 0

             FI;

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0;

VPBLENDMD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no controlmask*

     THEN

             IF (EVEX.b = 1) AND (SRC2 *is memory*)

                  THEN

                    DEST[i+31:i] := SRC2[31:0]

                  ELSE

                    DEST[i+31:i] := SRC2[i+31:i]

             FI;

     ELSE

             IF *merging-masking*                 ; merging-masking

                  THEN DEST[i+31:i] := SRC1[i+31:i]

                  ELSE                            ; zeroing-masking

                    DEST[i+31:i] := 0

             FI;

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPBLENDMD __m512i _mm512_mask_blend_epi32(__mmask16 k, __m512i a, __m512i b);
VPBLENDMD __m256i _mm256_mask_blend_epi32(__mmask8 m, __m256i a, __m256i b);
VPBLENDMD __m128i _mm_mask_blend_epi32(__mmask8 m, __m128i a, __m128i b);
VPBLENDMQ __m512i _mm512_mask_blend_epi64(__mmask8 k, __m512i a, __m512i b);
VPBLENDMQ __m256i _mm256_mask_blend_epi64(__mmask8 m, __m256i a, __m256i b);
VPBLENDMQ __m128i _mm_mask_blend_epi64(__mmask8 m, __m128i a, __m128i b);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-51, "Type E4 Class Exception Conditions."

Sources