Vesta
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Source code

KXNORW, KXNORB, KXNORQ, KXNORD

Bitwise Logical XNOR Masks

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
VEX.L1.0F.W0 46 /rKXNORW k1, k2, k3RVRValidValidBitwise XNOR 16-bit masks k2 and k3 and place result in k1. OR AVX10.1
VEX.L1.66.0F.W0 46 /rKXNORB k1, k2, k3RVRValidValidBitwise XNOR 8-bit masks k2 and k3 and place result in k1. OR AVX10.1
VEX.L1.0F.W1 46 /rKXNORQ k1, k2, k3RVRValidValidBitwise XNOR 64-bit masks k2 and k3 and place result in k1. OR AVX10.1
VEX.L1.66.0F.W1 46 /rKXNORD k1, k2, k3RVRValidValidBitwise XNOR 32-bit masks k2 and k3 and place result in k1. OR AVX10.1

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RVR

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

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Description

Performs a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1 (three-operand form).

Operation

KXNORW
DEST[15:0] := NOT (SRC1[15:0] BITWISE XOR SRC2[15:0])
DEST[MAX_KL-1:16] := 0

KXNORB
DEST[7:0] := NOT (SRC1[7:0] BITWISE XOR SRC2[7:0])
DEST[MAX_KL-1:8] := 0

KXNORQ
DEST[63:0] := NOT (SRC1[63:0] BITWISE XOR SRC2[63:0])
DEST[MAX_KL-1:64] := 0

KXNORD
DEST[31:0] := NOT (SRC1[31:0] BITWISE XOR SRC2[31:0])
DEST[MAX_KL-1:32] := 0

Intel C/C++ compiler intrinsics

KXNORW __mmask16 _mm512_kxnor(__mmask16 a, __mmask16 b);

Flags affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, "TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)."

Sources